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Fresh Grad Lands Job as Real Estate Agent With Help from Professional Writers

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Quiz 6 Interrupts PSW Registers

Navigation   » List of Schools  »  California State University, Northridge  »  Computer  »  Computer 222 – Computer Organization  »  Fall 2021  »  Quiz 6 Interrupts PSW Registers

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Below are the questions for the exam with the choices of answers:

Question #1
A stable system clock will help keep any digital system:
A  Indifferent
B  Clocked
C  Synchronized
D  Asynchronous
Question #2
What is used to distribute a system clock to all of the system:
A  Control bus
B  Registers
C  Quartz crystal
D  PLL tree
Question #3
What type of analog circuit is necessary for providing a stable clock:
A  PLL, including a VCXO
B  ALU
C  D flip-flops
D  Inductors
Question #4
What type of logic block is necessary for an FSM – Finite State Machine:
A  Latches
B  ALU
C  Decoders
D  Registers
Question #5
Which clocking scheme helps keep a digital system tightly synchronized (even used in the i8080):
A  Rising-edge clocking
B  Falling-edge clocking
C  2-phase clocking
D  Single-phase clocking
Question #6
Which sequential logic element is clock-edge triggered:
A  NAND gates
B  Flip-flops
C  Latches
D  ALU
Question #7
Registers are composed of a linear array of what logic element:
A  D flip-flops
B  NAND gates
C  ALU
D  RS latches
Question #8
MIPS CP0 contains which registers:
A  BadVAddr + Config, EPC + Count, and Cause + Status
B  Cause + Status
C  EPC + Count
D  BadVAddr + Config
Question #9
MIPS CP0 contains a Cause register, which contains:
A  Exception code + interrupts pending
B  Endianness control
C  Interrupt enables
D  Exception code only
Question #10
MIPS PSW contains:
A  Interrupt enables, Status register, and Flags
B  Status register
C  Interrupt enables
D  Flags
Question #11
PSW contains:
A  Program Software
B  Priority Sequence Word
C  Process Software
D  Program Status Word
Question #12
Interrupts are processed if what conditions are met:
A  Enabled and pre-emptive
B  Vectored with vector present on data bus
C  Pending and maskable
D  Mask and global enable bits are set, it is pending and highest priority
Question #13
What is an Interrupt Vector:
A  A byte that can be used by an ISR as a branch target offset
B  A byte that can be used by an ISR as a branch target offset, a byte provided by an interrupting device to identify itself, and a byte used by an ISR to decode the identity of an interrupting device
C  A byte provided by an interrupting device to identify itself
D  A byte used by an ISR to decode the identity of an interrupting device
Question #14
Low priority devices should use what class of Interrupt:
A  Non-Vectored
B  Maskable
C  Vectored
D  NMI
Question #15
Interrupts have all these properties, except:
A  A sub-class of Exception
B  Cause no pipeline flush
C  Preemption
D  Priority
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Manush
Fresh Graduate
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