Midterm Exam

Navigation » List of Schools » California State University, Northridge » Computer » Computer 222 – Computer Organization » Fall 2021 » Midterm Exam

Need help with your exam preparation?

Existing Quiz Clients Login here

Below are the questions for the exam with the choices of answers:

Try The Exam

Question #1

ARM v8 was redesigned from v7 to be more like:

A Apple A12X

B IA-64

C ARMv5

D MIPS

Question #2

Any PSW contains:

A Flags

B Interrupt enables

C Flags, Status bits, and Interrupt enables

D Status bits

Question #3

Multi-level memory hierarchy from fastest to slowest:

A Disk to Main to L2 cache

B General Registers to L1 cache to L2 cache

C Main to L2 cache to L1

D L1 cache to L2 cache to L1 cache

Question #4

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A addi, add

B addu, add

C add, adds

D addu, addu

Question #5

An SoC (like the Apple A13/14) can contain which functional elements:

A CPU + GPU cores

B Any of these

C L1 and L2 caches

D NPU cores + ML unit

Question #6

CPU’s Execution Unit contains all these:

A ALU + registers

B CPU + GPU

C ICU + PSW

D ALU + ICU + registers

Question #7

At the Macro architecture level, we address all of which units:

A ICU + ALU + Registers

B Just CPU cores

C Cores and caches

D Just GPU’s

Question #8

J-format is used for which MIPS instruction:

A la

B bne

C addi

D jal

Question #9

I-format is used for which MIPS instruction:

A div

B jal

C lui

D addu

Question #10

R-format is used for which MIPS instruction:

A subi

B bgtz

C addi

D add

Question #11

In general, any level cache may use which form of mapping:

A Any of these

B Fully associative

C Direct

D Set associative

Question #12

A CPU’s store word instruction will write a data word to (with write-though policy):

A L1 D-cache

B Main memory

C Main memory, L1 D-cache, and L2 cache

D L2 cache

Question #13

CPU General Registers are loaded directly from:

A L2 cache

B L3 cache

C L1 I-cache

D L1 D-cache

Question #14

Which register is not a GR in MIPS, but is a GR in ARMv5:

A PC

B SP

C $a0

D PSR

Question #15

For MIPS, where are the C, V, N, Z flags located:

A CPU GR

B CP1 $f2

C CP0 Status register

D CPU Cause register

Question #16

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A GPU

B up to 4 co-processors

C CP0 + CP1

D FPU

Question #17

x86 is what kind of architecture:

A General register

B Dedicated register

C Mixed register

D Load-Store

Question #18

An x86 CPU, 32-bit contains:

A SI, DI, CS, SS registers

B 32-bit ALU

C EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

D EAX, EBX, ECX, EDX registers

Question #19

A CPU core contains which blocks:

A L1 caches + Registers

B ALU + Registers

C ALU + L2 cache

D Execution Unit + L1 caches

Question #20

Currenty used ISA’s include these:

A MIPSV, ARMv7, x86-64, RISC IV

B MIPS64, ARMv8, IA-32, RISC V

C MIPSIII, ARMv5, IA-32, RISC V

D MIPS32, ARMv6, x86-32, RISC III

Question #21

MIPS primitives that ARMv7 does not have:

A mult, div

B beq, bgtz

C addi, subi

D syscall, break, lui

Question #22

ARMv7 primitives that MIPS does not have:

A push, bkpt, dbg

B call, jump

C addi, subi

D syscall, lui

Question #23

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A 224

B 16,384

C 1023

D 4095

Question #24

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A -32,768 to 32,767

B -256 to 255

C -65,565 to 65,564

D -16,383 to 16,384

Question #25

MIPS instruction: lw $r1,($r2) can address how much memory:

A 2 MB

B 1 GB

C 32 MiB

D 4 GiB

Try The Exam

Fresh Grad Lands Job as Real Estate Agent With Help from Professional Writers

Need help with your exam preparation?

Below are the questions for the exam with the choices of answers:

Manush

Christian S.

Tyra

Linda

Manush

Christian S.

Tyra

Linda

Manush

We accept payment