Midterm Exam

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Question #1

ARM v8 was redesigned from v7 to be more like:

A IA-64

B Apple A12X

C ARMv5

D MIPS

Question #2

Any PSW contains:

A Flags

B Flags, Status bits, and Interrupt enables

C Interrupt enables

D Status bits

Question #3

Multi-level memory hierarchy from fastest to slowest:

A Disk to Main to L2 cache

B General Registers to L1 cache to L2 cache

C Main to L2 cache to L1

D L1 cache to L2 cache to L1 cache

Question #4

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A add, adds

B addu, addu

C addi, add

D addu, add

Question #5

An SoC (like the Apple A13/14) can contain which functional elements:

A L1 and L2 caches

B CPU + GPU cores

C Any of these

D NPU cores + ML unit

Question #6

CPU’s Execution Unit contains all these:

A CPU + GPU

B ICU + PSW

C ALU + ICU + registers

D ALU + registers

Question #7

At the Macro architecture level, we address all of which units:

A Just GPU’s

B ICU + ALU + Registers

C Just CPU cores

D Cores and caches

Question #8

J-format is used for which MIPS instruction:

A la

B jal

C bne

D addi

Question #9

I-format is used for which MIPS instruction:

A jal

B lui

C addu

D div

Question #10

R-format is used for which MIPS instruction:

A subi

B add

C addi

D bgtz

Question #11

In general, any level cache may use which form of mapping:

A Direct

B Fully associative

C Any of these

D Set associative

Question #12

A CPU’s store word instruction will write a data word to (with write-though policy):

A L1 D-cache

B Main memory, L1 D-cache, and L2 cache

C L2 cache

D Main memory

Question #13

CPU General Registers are loaded directly from:

A L1 D-cache

B L1 I-cache

C L3 cache

D L2 cache

Question #14

Which register is not a GR in MIPS, but is a GR in ARMv5:

A SP

B $a0

C PSR

D PC

Question #15

For MIPS, where are the C, V, N, Z flags located:

A CPU Cause register

B CP0 Status register

C CPU GR

D CP1 $f2

Question #16

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A CP0 + CP1

B up to 4 co-processors

C GPU

D FPU

Question #17

x86 is what kind of architecture:

A General register

B Mixed register

C Dedicated register

D Load-Store

Question #18

An x86 CPU, 32-bit contains:

A 32-bit ALU

B EAX, EBX, ECX, EDX registers

C EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

D SI, DI, CS, SS registers

Question #19

A CPU core contains which blocks:

A ALU + L2 cache

B L1 caches + Registers

C Execution Unit + L1 caches

D ALU + Registers

Question #20

Currenty used ISA’s include these:

A MIPS64, ARMv8, IA-32, RISC V

B MIPS32, ARMv6, x86-32, RISC III

C MIPSIII, ARMv5, IA-32, RISC V

D MIPSV, ARMv7, x86-64, RISC IV

Question #21

MIPS primitives that ARMv7 does not have:

A mult, div

B addi, subi

C beq, bgtz

D syscall, break, lui

Question #22

ARMv7 primitives that MIPS does not have:

A syscall, lui

B addi, subi

C push, bkpt, dbg

D call, jump

Question #23

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A 4095

B 1023

C 16,384

D 224

Question #24

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A -256 to 255

B -32,768 to 32,767

C -65,565 to 65,564

D -16,383 to 16,384

Question #25

MIPS instruction: lw $r1,($r2) can address how much memory:

A 4 GiB

B 1 GB

C 32 MiB

D 2 MB

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