Midterm Exam

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Question #1

ARM v8 was redesigned from v7 to be more like:

A Apple A12X

B MIPS

C ARMv5

D IA-64

Question #2

Any PSW contains:

A Status bits

B Flags, Status bits, and Interrupt enables

C Flags

D Interrupt enables

Question #3

Multi-level memory hierarchy from fastest to slowest:

A Disk to Main to L2 cache

B Main to L2 cache to L1

C General Registers to L1 cache to L2 cache

D L1 cache to L2 cache to L1 cache

Question #4

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A addi, add

B addu, addu

C add, adds

D addu, add

Question #5

An SoC (like the Apple A13/14) can contain which functional elements:

A NPU cores + ML unit

B CPU + GPU cores

C L1 and L2 caches

D Any of these

Question #6

CPU’s Execution Unit contains all these:

A ALU + registers

B ALU + ICU + registers

C CPU + GPU

D ICU + PSW

Question #7

At the Macro architecture level, we address all of which units:

A Cores and caches

B Just CPU cores

C Just GPU’s

D ICU + ALU + Registers

Question #8

J-format is used for which MIPS instruction:

A la

B bne

C addi

D jal

Question #9

I-format is used for which MIPS instruction:

A div

B addu

C jal

D lui

Question #10

R-format is used for which MIPS instruction:

A add

B bgtz

C addi

D subi

Question #11

In general, any level cache may use which form of mapping:

A Any of these

B Direct

C Set associative

D Fully associative

Question #12

A CPU’s store word instruction will write a data word to (with write-though policy):

A Main memory, L1 D-cache, and L2 cache

B L1 D-cache

C L2 cache

D Main memory

Question #13

CPU General Registers are loaded directly from:

A L1 D-cache

B L2 cache

C L3 cache

D L1 I-cache

Question #14

Which register is not a GR in MIPS, but is a GR in ARMv5:

A $a0

B PC

C SP

D PSR

Question #15

For MIPS, where are the C, V, N, Z flags located:

A CP0 Status register

B CPU GR

C CP1 $f2

D CPU Cause register

Question #16

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A FPU

B CP0 + CP1

C GPU

D up to 4 co-processors

Question #17

x86 is what kind of architecture:

A Dedicated register

B Load-Store

C General register

D Mixed register

Question #18

An x86 CPU, 32-bit contains:

A 32-bit ALU

B SI, DI, CS, SS registers

C EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

D EAX, EBX, ECX, EDX registers

Question #19

A CPU core contains which blocks:

A Execution Unit + L1 caches

B ALU + Registers

C L1 caches + Registers

D ALU + L2 cache

Question #20

Currenty used ISA’s include these:

A MIPSIII, ARMv5, IA-32, RISC V

B MIPS32, ARMv6, x86-32, RISC III

C MIPSV, ARMv7, x86-64, RISC IV

D MIPS64, ARMv8, IA-32, RISC V

Question #21

MIPS primitives that ARMv7 does not have:

A mult, div

B addi, subi

C syscall, break, lui

D beq, bgtz

Question #22

ARMv7 primitives that MIPS does not have:

A push, bkpt, dbg

B addi, subi

C call, jump

D syscall, lui

Question #23

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A 1023

B 4095

C 224

D 16,384

Question #24

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A -32,768 to 32,767

B -256 to 255

C -16,383 to 16,384

D -65,565 to 65,564

Question #25

MIPS instruction: lw $r1,($r2) can address how much memory:

A 1 GB

B 2 MB

C 32 MiB

D 4 GiB

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