Midterm Exam

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Question #1

ARM v8 was redesigned from v7 to be more like:

A ARMv5

B IA-64

C Apple A12X

D MIPS

Question #2

Any PSW contains:

A Flags

B Flags, Status bits, and Interrupt enables

C Status bits

D Interrupt enables

Question #3

Multi-level memory hierarchy from fastest to slowest:

A L1 cache to L2 cache to L1 cache

B Disk to Main to L2 cache

C Main to L2 cache to L1

D General Registers to L1 cache to L2 cache

Question #4

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A addi, add

B addu, add

C addu, addu

D add, adds

Question #5

An SoC (like the Apple A13/14) can contain which functional elements:

A L1 and L2 caches

B NPU cores + ML unit

C Any of these

D CPU + GPU cores

Question #6

CPU’s Execution Unit contains all these:

A ICU + PSW

B ALU + ICU + registers

C ALU + registers

D CPU + GPU

Question #7

At the Macro architecture level, we address all of which units:

A ICU + ALU + Registers

B Just CPU cores

C Cores and caches

D Just GPU’s

Question #8

J-format is used for which MIPS instruction:

A la

B jal

C addi

D bne

Question #9

I-format is used for which MIPS instruction:

A jal

B addu

C div

D lui

Question #10

R-format is used for which MIPS instruction:

A addi

B subi

C add

D bgtz

Question #11

In general, any level cache may use which form of mapping:

A Any of these

B Set associative

C Direct

D Fully associative

Question #12

A CPU’s store word instruction will write a data word to (with write-though policy):

A Main memory, L1 D-cache, and L2 cache

B L1 D-cache

C Main memory

D L2 cache

Question #13

CPU General Registers are loaded directly from:

A L1 D-cache

B L3 cache

C L1 I-cache

D L2 cache

Question #14

Which register is not a GR in MIPS, but is a GR in ARMv5:

A PSR

B SP

C $a0

D PC

Question #15

For MIPS, where are the C, V, N, Z flags located:

A CP0 Status register

B CPU GR

C CP1 $f2

D CPU Cause register

Question #16

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A CP0 + CP1

B GPU

C FPU

D up to 4 co-processors

Question #17

x86 is what kind of architecture:

A Load-Store

B General register

C Mixed register

D Dedicated register

Question #18

An x86 CPU, 32-bit contains:

A EAX, EBX, ECX, EDX registers

B 32-bit ALU

C SI, DI, CS, SS registers

D EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

Question #19

A CPU core contains which blocks:

A ALU + L2 cache

B ALU + Registers

C L1 caches + Registers

D Execution Unit + L1 caches

Question #20

Currenty used ISA’s include these:

A MIPSV, ARMv7, x86-64, RISC IV

B MIPS64, ARMv8, IA-32, RISC V

C MIPS32, ARMv6, x86-32, RISC III

D MIPSIII, ARMv5, IA-32, RISC V

Question #21

MIPS primitives that ARMv7 does not have:

A mult, div

B addi, subi

C beq, bgtz

D syscall, break, lui

Question #22

ARMv7 primitives that MIPS does not have:

A call, jump

B addi, subi

C push, bkpt, dbg

D syscall, lui

Question #23

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A 224

B 16,384

C 4095

D 1023

Question #24

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A -65,565 to 65,564

B -32,768 to 32,767

C -16,383 to 16,384

D -256 to 255

Question #25

MIPS instruction: lw $r1,($r2) can address how much memory:

A 2 MB

B 1 GB

C 32 MiB

D 4 GiB

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